High-speed serial link channels delivering an effective data rate above 5 Gb/s in a backplane environment are subject to significant signal distortion due to inter-symbol interference (ISI). Transmitters and receivers need to compensate most of the signal distortion using very low complexity schemes in order to obtain a target bit error rate (BER) of less than or equal to 10−17 at Gb/s rates and under severe power and complexity restrictions. This constrained space presents significant challenges to well-known signal processing and coding techniques, and sub-optimal but efficient alternatives are sometimes needed to fulfill the task.
Attenuation caused by conductor and dielectric losses causes dispersion ISI. Another important ISI component is reflections, which are essentially multipath components of a signal and originate from impedance discontinuities such as those caused by connectors of line cards at both transmit and receive ends. In addition to ISI distortion, cross-talk effects from far and near end adjacent channels is becoming increasingly significant.
To counteract channel attenuation at high bit rates, 4-level pulse amplitude modulation (4-PAM) signaling is often used instead of conventional 2-level pulse amplitude modulation (2-PAM) signaling. That is, in a 2-PAM signaling system, each conductor in the system may carry signals at one of two signal levels (i.e., at either a logic zero level or a logic one level). Thus, in a 2-PAM signaling system, each conductor in the system can only transmit one bit of data at a time. However, in a 4-PAM signaling system, each conductor in the system may carry signals at four different signal levels (i.e., four different symbols). Thus, in a 4-PAM signaling system, each conductor in the system can transmit two bits of data simultaneously at half of the symbol rate for an equivalent bandwidth.
In a 4-PAM signaling system that uses current-based output drivers, the four different signal levels are represented by different current values. For example, the four different current levels may be identified as 0i, 1i, 2i, and 3i. Similarly, in a 4-PAM transmission system that uses voltage-based output drivers, the four different signal levels are represented by different voltage values. For example, the four different voltage levels may be identified as 0v, 1v, 2v, and 3v. Both of these types of output drivers are typically connected in a transmission line environment that presents an effective resistance or impedance to the output driver. This transmission line impedance causes the output voltage to change if the output current from the current driver changes, and causes the output current to change if the output voltage from the voltage driver changes.
A 4-PAM signaling system may be used in systems having either differential pairs of signals or single-ended signals referenced to ground. In a 4-PAM signaling system utilizing many single-ended output drivers, it is desirable to maintain the total signal current required to transmit a byte of data (or code word) at a relatively constant current level in comparison to other bytes of data (or code words). If the signal current fluctuates greatly from one byte to the next, current changes flow through power supply connections and cause noise. These current changes occur when using either voltage drivers or current drivers. The noise on the power supply increases in systems that have high data transmission rates and fast edge rate transmitters. This noise on the power supply degrades the voltage margins of the signals.
Understandably, while advantageous in channels with dominant attenuation, 4-PAM signaling systems are more sensitive to reflections and cross-talk than 2-PAM signaling systems due to the reduction in signal margin as a result of carrying more information per symbol. Thus, in cases where high loss and reflections are combined, the advantages of 4-PAM signaling over 2-PAM signaling may be lost.
In order to preserve the advantages of 4-PAM signaling over 2-PAM signaling it would be desirable to eliminate full-swing transitions (FST) between sequential 4-PAM symbols. This could enhance system performance in terms of: 1.) voltage margins (Vm), by reducing peak distortion (PD) via the elimination of one or more worst case sequences; and 2.) timing margins (Tm), especially at outer eyes where FST close eyes the most.
It would also be desirable to secure a minimum density of desirable symbol transitions useful for clock recovery. These clock data recovery (CDR) transitions could prevent continuous phase drifting from an optimum sampling point at the center of an eye in plesiochronous systems with frequency offsets between received data and a local receive clock.
In view of the foregoing, it would be desirable to provide a technique for improving the quality of digital signals in a multi-level signaling system which overcomes the above-described inadequacies and shortcomings in an efficient and cost effective manner.